functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 250 mhz, voltage output 4-quadrant multiplier AD835 product description the AD835 is a complete four-quadrant voltage output analog multiplier fabricated on an advanced dielectrically isolated complementary bipolar process. it generates the linear product of its x and y voltage inputs, with a C3 db output bandwidth of 250 mhz (a small signal rise time of 1 ns). full-scale (C1 v to +1 v) rise/fall times are 2.5 ns (with the standard r l of 150 w ) and the settling time to 0.1% under the same conditions is typi- cally 20 ns. its differential multiplication inputs (x, y) and its summing in- put (z) are at high impedance. the low impedance output volt- age (w) can provide up to 2.5 v and drive loads as low as 25 w . normal operation is from 5 v supplies. though providing state-of-the-art speed, the AD835 is simple to use and versatile. for example, as well as permitting the addi- tion of a signal at the output, the z input provides the means to operate the AD835 with voltage gains up to about 10. in this capacity, the very low product noise of this multiplier (50 nv ? hz ) makes it much more useful than earlier products. the AD835 is available in an 8-pin plastic mini-dip package (n) and an 8-pin soic (r) and is specified to operate over the C40 c to +85 c industrial temperature range. product highlights 1. the AD835 is the first monolithic 250 mhz four quadrant voltage output multiplier. 2. minimal external components are required to apply the AD835 to a variety of signal processing applications. 3. high input impedances (100 k w i 2 pf) make signal source loading negligible. 4. high output current capability allows low impedance loads to be driven. 5. state of the art noise levels achieved through careful device optimization and the use of a special low noise bandgap volt- age reference. 6. designed to be easy to use and cost effective in applications which formerly required the use of hybrid or board level solutions. features simple: basic function is w = xy + z complete: minimal external components required very fast: settles to 0.1% of fs in 20 ns dc-coupled voltage output simplifies use high differential input impedance x, y and z inputs low multiplier noise: 50 nv/ ? hz applications very fast multiplication, division, squaring wideband modulation and demodulation phase detection and measurement sinusoidal frequency doubling video gain control and keying voltage controlled amplifiers and filters y1 y2 z input y = y1 ?2 x = x1 ?2 xy + z x1 x2 w output xy AD835 ? +1 ? analog devices, inc., 1994 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703
AD835Cspecifications model AD835an/ar transfer function w = ( x 1 x 2)( y 1 y 2) u + z parameter conditions min typ max unit input characteristics (x, y) differential voltage range v cm = 0 1v differential clipping level 6 1.2 1.4 v low frequency nonlinearity x = 1 v, y = 1 v 0.3 0.5 % fs y = 1 v, x = 1 v 0.1 0.3 % fs vs. temperature t min to t max 1 x = 1 v, y = 1 v 0.7 % fs y = 1 v, x = 1 v 0.5 % fs common-mode voltage range C2.5 +3 v offset voltage 3 6 20 mv vs. temperature t min to t max 1 25 mv cmrr f 100 khz; 1 v p-p 70 db bias current 10 20 m a vs. temperature t min to t max 1 27 m a offset bias current 2 m a differential resistance 100 k w single-sided capacitance 2pf feedthrough, x x = 1 v, y = 0 v C46 db feedthrough, y y = 1 v, x = 0 v C60 db dynamic characteristics C3 db small-signal bandwidth 150 250 mhz C0.1 db gain flatness frequency 15 mhz slew rate w = C2.5 v to +2.5 v 1000 v/ m s differential gain error, x f = 3.58 mhz 0.3 % differential phase error, x f = 3.58 mhz 0.2 degrees differential gain error, y f = 3.58 mhz 0.1 % differential phase error, y f = 3.58 mhz 0.1 degrees harmonic distortion x or y = 10 dbm, 2nd and 3rd harmonic fund = 10 mhz C70 db fund = 50 mhz C40 db settling time, x or y to 0.1%, w = 2 v p-p 20 ns summing input (z) gain from z to w, f 10 mhz 0.990 0.995 C3 db small-signal bandwidth 250 mhz differential input resistance 60 k w single sided capacitance 2pf maximum gain x, y to w, z shorted to w, f = 1 khz 50 db bias current 50 m a output characteristics voltage swing 2.2 2.5 v vs. temperature t min to t max 1 2.0 v voltage noise spectral density x = y = 0, f < 10 mhz 50 nv/ ? hz offset voltage 25 6 75 mv vs. temperature 2 t min to t max 1 10 mv short circuit current 75 ma scale factor error 5 6 8 % fs vs. temperature t min to t max 1 9 % fs linearity (relative error) 3 0.5 6 1.0 % fs vs. temperature t min to t max 1 1.25 % fs power supplies supply voltage for specified performance 4.5 5 5.5 v quiescent supply current 16 25 ma vs. temperature t min to t max 1 26 ma psrr at output vs. vp +4.5 v to +5.5 v 0.5 %/v psrr at output vs. vn C4.5 v to C5.5 v 0.5 %/v notes 1 t min = C40 c, t max = +85 c. 2 normalized to zero at +25 c. 3 linearity is defined as residual error after compensating for input offset, output voltage offset and scale factor errors. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. specifications subject to change without notice. rev. a C2C (t a = +25 8 c, v s = 6 5 v, r l = 150 v , c l 5 pf unless otherwise noted)
AD835 rev. a C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 300 mw operating temperature range . . . . . . . . . . . . . C40 c to +85c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature, soldering 60 sec . . . . . . . . . . . . . . +300 c esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500 v notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. 2 thermal characteristics: 8-pin plastic dip (n): q jc = 35 c/w; q ja = 90 c/w 8-pin plastic soic (r): q jc = 45 c/w; q ja = 115 c/w. pin connections 8-pin plastic dip (n) 8-pin plastic soic (r) y1 y2 vn z x1 x2 vp w 1 2 3 4 8 7 6 5 top view (not to scale) AD835 ordering guide model temperature range package options* AD835an C40 c to +85 c n-8 AD835ar C40 c to +85 c r-8 *n = plastic dip; r = small outline ic plastic package (soic). figure 1. typical composite output differential gain & phase, ntsc for x channel; f = 3.58 mhz, r l = 150 w figure 3. gain & phase vs. frequency of x, y, z inputs frequency ?hz 1g ?.2 ?.3 ?.4 ?.5 ?.6 ?.1 0 magnitude ?db x, y ch = odbm r l = 150 w c l 5pf 1m 10m 100m 300k figure 4. gain flatness to 0.1 db 0.20 ?.20 ?.10 0.10 0.00 0.03 0.00 0.16 0.10 0.07 0.04 0.01 0.00 ?.20 ?.01 0.00 ?.00 differential phase ?degrees differential gain ?% 2nd 1st 6th 5th 4th 3rd 2nd 1st 6th 5th 4th 3rd ?.3 0.0 ?.2 ?.1 0.2 0.3 0.1 min = ?.02 max = 0.01 p-p/max = 0.03 min = 0.00 max = 0.16 p-p = 0.16 dg dp (ntsc) field = 1 line = 18 wfm fcc composite 1m 10m 1g 100m ? ? ? ? ?0 0 2 magnitude ?db frequency ?hz phase ?degrees 0 ?0 ?80 90 180 phase x, y, z ch = 0dbm r l = 150 w c l 5pf gain figure 2. typical composite output differential gain & phase, ntsc for y channel; f = 3.58 mhz, r l = 150 w 0.4 ?.4 ?.2 0.2 0.0 0.02 0.00 0.06 0.03 0.03 0.02 0.06 0.00 0.20 0.19 0.16 0.11 differential phase ?degrees differential gain ?% 2nd 1st 6th 5th 4th 3rd 2nd 1st 6th 5th 4th 3rd ?.3 0.0 ?.2 ?.1 0.2 0.3 0.1 min = 0.00 max = 0.20 p-p/max = 0.20 min = 0.00 max = 0.06 p-p = 0.06 dg dp (ntsc) field = 1 line = 18 wfm fcc composite typical performance characteristics
AD835 rev. a C4C figure 7. large signal pulse response at w output, r l = 150 w , c l 5 pf, x channel = 1.0 v, y channel = 1.0 v ?0 ?0 ?0 ?0 ?0 ?0 magnitude ?db frequency ?hz 1m 10m 1g 100m x feedthrough y feedthrough x feedthrough y feedthrough x, y ch = 5dbm r l = 150 w c l < 5pf figure 6. small signal pulse response at w output, r l = 150 w , c l 5 pf, x channel = 0.2 v, y channel = 1.0 v 500mv 1v gnd ?v 10ns figure 9. psrr vs. frequency for v+ and vC supply figure 10. harmonic distortion at 10 mhz; 10 dbm input to x or y channels, r l = 150 w , c l = 5 pf ?0 ?0 ?0 ?0 ?0 ?0 psrr ?db frequency ?hz 1m 10m 1g 100m 300k psrr on v+ psrr on v 0dbm on supply x, y = 1v 60 80 0 40 20 cmrr ?db frequency ?hz 1m 10m 1g 100m figure 8. cmrr vs. frequency for x or y channel, r l = 150 w , c l 5 pf figure 5. x and y feedthrough vs. frequency 100mv 0.200v gnd ?.200v 10ns 10mhz 20mhz 30mhz 10db/div
AD835 rev. a C5C figure 16. fixed if vs. lo frequency on y channel figure 12. harmonic distortion at 100 mhz, 10 dbm input to x or y channel, r l = 150 w , c l 5 pf figure 15. fixed lo on y channel vs. rf frequency input to x channel 50mhz 100mhz 150mhz 10db/div 15 ?5 ?0 0 5 10 ? 125 ?5 ?5 45 25 5 ?5 105 85 65 temperature ? c v os output drift ?mv output v os drift, normalized to 0 at 25 c output offset drift will typically be within shaded area figure 14. v os output drift vs. temperature figure 11. harmonic distortion at 50 mhz, 10 dbm input to x or y channel, r l = 150 w , c l 5 pf 100mhz 200mhz 300mhz 10db/div 1v 10ns +2.5v gnd ?.5v figure 13. maximum output voltage swing, r l = 50 w , c l 5 pf 35 0 15 5 10 20 25 30 200 20 0 180 160 80 60 40 140 120 100 lo frequency on y ch ?mhz 3rd order intercept ?dbm x ch = 6dbm y ch = 10dbm r l = 100 w 35 0 15 5 10 20 25 30 200 20 0 180 160 80 60 40 140 120 100 rf frequency input x channel ?mhz 3rd order intercept ?dbm x ch = 6dbm y ch = 10dbm r l = 100 w
AD835 rev. a C6C simplified representations of this sort, where all signals are pre- sumed to be expressed in volts , are used throughout this data sheet, to avoid the needless use of less-intuitive subscripted vari- ables (such as v x1 ). we can view all variables as being normal- ized to 1 v . for example, the input x can either be stated as being in the range C1 v to +1 v, or simply C1 to +1. the latter representation will be found to facilitate the development of new functions using the AD835. the explicit inclusion of the de- nominator, u, is also less helpful, as in the case of the AD835, if it is not an electrical input variable. scaling adjustment the basic value of u in equation 1 is nominally 1.05 v. figure 18, which shows the basic multiplier connections, also shows how the effective value of u can be adjusted to have any lower voltage (usually 1 v) through the use of a resistive-divider between w (pin 5) and z (pin 4). using the general resistor val- ues shown, we can rewrite equation 1 as w = xy u + kw + (1 k ) z ? (3) (where z' is distinguished from the signal z at pin 4). it follows that (4) in this way, we can modify the effective value of u to u ? = (1 k ) u (5) without altering the scaling of the z' input. (this is to be ex- pected, since the only ground reference for the output is through the z' input.) thus, to set u' to 1 v, remembering that the basic value of u is 1.05 v, we need to choose r1 to have a nominal value of 20 times r2. the values shown here allow u to be adjusted through the nominal range 0.95 v to 1.05 v, that is, r2 pro- vides a 5% gain adjustment. figure 18. multiplier connections note that in many applications, the exact gain of the multiplier may not be very important; in which case, this network may be omitted entirely, or r2 fixed at 100 w . product description the AD835 is a four-quadrant, voltage output, analog multi- plier fabricated on an advanced, dielectrically isolated, comple- mentary bipolar process. in its basic mode, it provides the linear product of its x and y voltage inputs. in this mode, the C3 db output voltage bandwidth is 250 mhz (a small signal rise time of 1 ns). full-scale (C1 v to +1 v) rise/fall times are 2.5 ns (with the standard r l of 150 w ) and the settling time to 0.1% under the same conditions is typically 20 ns. as in earlier multipliers from analog devices, a unique sum- ming feature is provided at the z-input. as well as providing in- dependent ground references for inputs and output, and enhanced versatility, this feature allows the AD835 to operate with voltage gain . its x-, y- and z-input voltages are all nomi- nally 1 v fs, with overrange of at least 20%. the inputs are fully differential and at high impedance (100 k w i 2 pf) and pro- vide a 70 db cmrr (f 1 mhz). the low impedance output is capable of driving loads as small as 25 w . the peak output can be as large as 2.2 v minimum for r l = 150 w , or 2.0 v minimum into r l = 50 w . the AD835 has much lower noise than the ad534 or ad734, mak- ing it attractive in low level signal-processing applications, for example, as a wideband gain-control element or modulator. basic theory the multiplier is based on a classic form, having a translinear core, supported by three (x, y, z) linearized voltage-to-current converters, and the load driving output amplifier. the scaling voltage (the denominator u, in the equations below) is provided by a bandgap reference of novel design, optimized for ultralow noise. figure 17 shows the functional block diagram. in general terms, the AD835 provides the function w = ( x 1 x 2)( y 1 y 2) u + z (1) where the variables w, u, x, y and z are all voltages. con- nected as a simple multiplier, with x = x1 C x2, y = y1 C y2 and z = 0, and with a scale factor adjustment (see below) which sets u = 1 v, the output can be expressed as w=xy (2) figure 17. functional block diagram y1 y2 z input y = y1 ?2 x = x1 ?2 xy + z x1 x2 w output xy AD835 ? +1 w = xy (1 k ) u + z ? r1 = (1?) r 2k w w r2 = kr 200 w +5v +5v x1 x2 vp w z vn y2 y1 x1 AD835 fb +5v x y ?v z 1 fb 3 4 2 1 5 7 0.01 m f ceramic 4.7 m f tantalum 8 0.01 m f ceramic 4.7 m f tantalum 6
AD835 rev. a C7C applications the AD835 is both easy to use and versatile. the capability for adding another signal to the output at the z input is frequently valuable. three applications of this feature are presented here: a wideband voltage controlled amplifier, an amplitude modulator and a frequency doubler. of course, the AD835 may also be used as a square law detector (with its x- and y-inputs con- nected in parallel) in which mode it is useful at input frequen- cies to well over 250 mhz, since that is the bandwidth limitation only of the output amplifier . multiplier connections figure 18 shows the basic connections for multiplication. the inputs will often be single sided, in which case the x2 and y2 inputs will normally be grounded. note that by assigning pins 7 and 2 to these (inverting) inputs, respectively, an extra measure of isolation between inputs and output is provided. the x and y inputs may, of course, be reversed to achieve some desired overall sign with inputs of a particular polarity, or they may be driven fully differentially. power supply decoupling and careful board layout are always important in applying wideband circuits. the decoupling rec- ommendations shown in figure 18 should be followed closely. in remaining figures in this data sheet, these power supply decoupling components have been omitted for clarity, but should be used wherever optimal performance with high speed inputs is required. however, they may be omitted if the full high frequency capabilities of AD835 are not being exploited. a wideband voltage controlled amplifier figure 19 shows the AD835 configured to provide a gain of nominally 0 to 12 db. (in fact, the control range extends from well under C12 db to about +14 db.) r1 and r2 set the gain to be nominally 4. the attendant bandwidth reduction that comes with this increased gain can be partially offset by the ad- dition of the peaking capacitor c1. although this circuit shows the use of dual supplies, the AD835 can operate from a single 9 v supply with slight revision. figure 19. voltage controlled 50 mhz amplifier using the AD835 the ac response of this amplifier for gains of 0 db (v g = 0.25 v), 6 db (v g = 0.5 v) and 12 db (v g = 1 v) is shown in figure 20. in this application, the resistor values have been slightly adjusted to reflect the nominal value of u = 1.05 v. the overall sign of the gain may be controlled by the sign of v g . v in (signal) r2 301 w voltage output x1 x2 vp w z vn y2 y1 x1 AD835 +5v ?v r1 97.6 w 3 4 2 1 5 6 7 8 c1 33pf v g (gain control) figure 20. ac response of vca an amplitude modulator figure 21 shows a simple modulator. the carrier is applied both to the y-input and the z-input, while the modulating signal is applied to the x-input. for zero modulation, there is no product term, so the carrier input is simply replicated at unity gain by the voltage follower action from the z-input. at x = 1 v, the rf output is doubled, while for x = C1 v, it is fully suppressed. that is, an x-input of approximately 1 v (actually u, or about 1.05 v) corresponds to a modulation index of 100%. car- rier and modulation frequencies can be up to 300 mhz, some- what beyond the nominal C3 db bandwidth. of course, a suppressed carrier modulator can be implemented by omitting the feedforward to the z-input, grounding that pin instead. figure 21. simple amplitude modulator using the AD835 squaring and frequency doubling amplitude domain squaring of an input signal, e, is achieved simply by connecting the x- and y-inputs in parallel to pro- duce an output of e 2 /u. the input may have either polarity, but the output in this case will always be positive. the output polar- ity may be reversed by interchanging either the x or y inputs. when the input is a sine wave e sin w t, a signal squarer behaves as a frequency doubler, since (6) while useful, equation 6 shows a dc term at the output which will vary strongly with the amplitude of the input, e. modulated carrier output modulation input carrier output x1 x2 vp w z vn y2 y1 x1 AD835 +5v ?v 3 4 2 1 5 6 7 8 e sin w t () 2 u = e 2 2 u (1 cos 2 w t ) 100k 100m 10m 1m 10k 12db (v g = 1v) 0db (v g = 0.25v) 6db (v g = 0.5v) start 10 000.000hz stop 100 000 000.000hz
AD835 rev. a C8C outline dimensions dimensions shown in inches and (mm). 8-pin plastic dip (n package) 8-pin plastic soic (r package) pin 1 0.280 (7.11) 0.240 (6.10) 4 5 8 1 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) seating plane 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) min 0.210 (5.33) max 0.160 (4.06) 0.115 (2.93) 0.430 (10.92) 0.348 (8.84) 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15) 0.022 (0.558) 0.014 (0.356) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 4 5 1 8 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 0.0098 (0.25) 0.0040 (0.10) 0.1968 (5.00) 0.1890 (4.80) 0.102 (2.59) 0.094 (2.39) 0.0500 (1.27) bsc 0.0192 (0.49) 0.0138 (0.35) figure 22 shows a frequency doubler which overcomes this limi- tation and provides a relatively constant output over a moder- ately wide frequency range, determined by the time-constant c1 and r1. the voltage applied to the x- and y-inputs are exactly in quadrature at a frequency f = 1/2 p c1r1 and their ampli- tudes are equal. at higher frequencies, the x-input becomes smaller while the y-input increases in amplitude; the opposite happens at lower frequencies. the result is a double frequency output, centered on ground, whose amplitude of 1 v for a 1 v input varies by only 0.5% over a frequency range of 10%. be- cause there is no squared dc component at the output, sud- den changes in the input amplitude do not cause a bounce in the dc level. figure 22. broadband zero-bounce frequency doubler this circuit is based on the identity cos q sin q= 1 2 sin 2 q ( 7) at w o = 1/c1r1, the x input leads the input signal by 45 (and is attenuated by ? 2 , while the y input lags the input signal by 45 , and is also attenuated by ? 2. since the x and y inputs are 90 out of phase, the response of the circuit will be w = 1 u e 2 (sin w t 45 ) e 2 (sin w t + 45 ) = e 2 2 u (sin 2 w t ) (8) which has no dc component, r2 and r3 are included to restore the output to 1 v for an input amplitude of 1 v (the same gain adjustment as mentioned earlier). because the voltage across the capacitor, c1, decreases with frequency, while that across the resistor, r1, increases, the amplitude of the output varies only slightly with frequency. in fact, it is only 0.5% below its full value (at its center frequency w o = 1/c1r1) at 90% and 110% of this frequency. r1 r3 301 w voltage output x1 x2 vp w z vn y2 y1 x1 AD835 +5v ?v r2 97.6 w 3 4 2 1 5 6 7 8 c1 v g printed in u.s.a. c1903aC3C12/94
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